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Flexible static memory controller (FSMC)
RM0008
Table 91.
Non muxed I/Os PSRAM (continued)
FSMC signal name
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1]
NBL[0]
I/O
O
O
O
O
I
O
O
Function
Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
Output enable
Write enable
Address valid PSRAM input (memory signal name: NADV)
PSRAM wait input signal to the FSMC
Upper byte enable (memory signal name: NUB)
Lowed byte enable (memory signal name: NLB)
PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
19.5.2
Supported memories and transactions
Table 92 below displays the supported devices, access modes and transactions.
Transactions not allowed (or not supported) by the FSMC appear in gray.
Table 92.
NOR Flash/PSRAM supported memories and transactions
Device
NOR Flash
Mode
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
R/W
R
W
R
W
R
AHB
data
size
8
8
16
16
32
Memory
data size
16
16
16
16
16
Allowed/
not
allowed
Y
N
Y
Y
Y
Comments
Split into 2 FSMC
accesses
(muxed I/Os
and nonmuxed Asynchronous
I/Os)
Asynchronous
page
Synchronous
Synchronous
Synchronous
W
R
R
R
R
32
-
8
16
32
16
16
16
16
16
Y
N
N
Y
Y
Split into 2 FSMC
accesses
Mode is not supported
416/995
Doc ID 13902 Rev 9
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